This invention relates to a phase-locked loop for generating the fundamental clock period in a binary data pulse train as it is read from a magnetic storage medium, and more particularly to an improvement in the phase error detection portion of the loop.
An improved phase-locked loop (PLL) has been disclosed in U.S. Pat. No. 3,944,940. In that PLL, coincidence gating means are employed for phase error detection between a feedback pulse train and a read pulse train. The feedback pulse train is generated by a voltage controlled oscillator (VCO) driving a single stage binary counter. The central frequency of the VCO is twice the nominal frequency of the read pulse train so that the output of the single stage binary counter is a squarewave signal at the nominal frequency of the read pulse train. The true output of the binary counter is compared with the phase of the read pulse train in one gate of the coincidence gating means while the complementary output of the binary counter is compared with the phase of the read pulse train in a second gate of the coincidence gating means.
The read pulses are shaped to have a pulse width approximately one quarter of a data bit period of double-frequency data modulation where a bit 1 pulse is recorded in the second half of a bit cell and a clock pulse is recorded in the first half. Only the clock pulse is recorded in the first half of a bit cell for a bit 0. Upon reading the recorded data and interlaced clock pulses, a train of read pulses is produced in which the clock pulses interlaced with data pulses appear like the data pulses in one half of a data cell period, each read pulse having a controlled pulse width equal to one quarter of a data cell period. The pulses in the read pulse train produce pulses of equal pulse width at the output of the two phase detection gates when the phase of the pulses read is precisely one-eighth of a data cycle out of phase with respect to the squarewave feedback signal. Any shift of the phase relationship between the read pulse period and the feedback pulse period through .+-.45.degree. (.+-.1/8 data period) will increase the width of the output pulse from one gate while decreasing the width of the output pulse from the other gate by a corresponding amount. Consequently, upon filtering the output pulses of the gates, there will be produced two DC signals. The difference between the two DC signals is linearly proportional to the phase error, and the sign of the difference will correspond to the polarity (direction) of the phase error. The difference signal can be used to acquire and maintain synchronization between the read pulse train and the feedback pulses.
For a data period phase error in the range from +45.degree. to -45.degree., the sign (polarity) of the phase error signal is set to drive the frequency of the VCO in a direction that will restore the phase relationship. In addition, the magnitude of the phase error signal increases linearly with phase error. Once the phase error exceeds .+-.45.degree., the sign (polarity) of the phase error signal remains correct. However, the magnitude of the phase error signal decreases linearly with increasing phase error from 45.degree. to 90.degree., making synchronization improbable.
For double-frequency recording, a phase shift in the feedback pulses through half a data cell period is of no consequence because the feedback pulses are symmetrical. In other words, since every feedback pulse is equal to half the feedback pulse period, it matters not which pulse is synchronized with the data pulse as between two successive feedback pulses occurring during the same data bit period. However, a problem arises if the density of the data pulses is increased, such as from 2200 bits per inch to 4400 bits per inch (BPI).
If the same double-frequency recording scheme is to be employed for the higher data density (4400 BPI), the bandwidth of the PLL must be increased correspondingly. Although that could be achieved, there would still be a problem of bit density on the media, i.e., 4400 bits per inch recorded with the double-frequency technique requires 8800 pulses per inch. At such high pulse rates, the physical size of the gap in the read and write heads becomes a very significant factor.
To avoid such a high recording pulse rate in a higher bit density system, a modified frequency modulation (MFM) recording scheme may be used in which the flux state is changed a maximum of once in a data cell period. If the recording of a data cell is controlled during four evenly spaced intervals such that the state of the flux is of a given polarity an even number of intervals, namely two, a bit 1 is recorded; and if the state of the flux is of the given polarity an odd number of intervals, namely one or three, a bit 0 is recorded. This flux pattern could, of course, be reversed in so far as the bits represented are concerned, but in either case, the read pulse pattern produced will have a maximum of one pulse per data cell period, each pulse being shaped to be one half a data pulse period. If the same phase-locked loop is now employed as for the 2200 BPI double-frequency recording scheme, the dynamic range of the PLL must be increased because a phase error of .+-.45.degree. in terms of a data cell period for double-frequency recording becomes a phase error of .+-..pi..degree. for MFM recording. The dynamic range requirements are thus increased from 90.degree. to 180.degree.. The problem then is to increase the dynamic range of the PLL of the double-frequency recording system from .+-.45.degree. to .+-.90.degree. for use in an MFM recording system of doubled bit density without increasing the band-width of the PLL.